1. Field of the Invention
The present invention relates to a level shift amplifier shifting the fine amplitude voltage to the full amplitude voltage, and more particularly, to an amplifier applicable to a sense amplifier reading the cell output voltage of semiconductor memories.
2. Description of the Related Art
Recently, as required for the high-performance of various information processing devices, sense amplifiers detecting the cell output voltage of semiconductor memories at high speed have been developed.
According to the above development, a latch type sense amplifier amplifying the fine potential difference by shifting its level or a current mirror type sense amplifier reading at high speed the cell output voltage are utilized. However, because the amplification factor of the former amplifier falls unless its input signal is within the specified area, it is not for practical use as a sense amplifier. Also the latter amplifier with its latch function causes to enlarge the signal potential difference, which necessitates the time to reset it.
Prior arts concerning the present invention are described as below. For one example, the level shift amplifier as shown in The Institute of Electronics, Information and Communication Engineers, 1992 Spring National Convention C-567 (hereinafter called "the first level shift amplifier") is applicable to the sense amplifier 4 reading the cell output voltage concerning the semiconductor memory device as shown FIG. 1. The semiconductor memory device comprises a word decoder 1, a memory cell 2, a writing circuit 3 and a sense amplifier 4.
The sense amplifier 4 also comprises a p type field effect transistor TP, n type field effect transistors TN1 and TN2, a CMOS inverter 4B, and a reference voltage source 4A. Transistors TP, TN1, and TN2 connected in series between a source line VCC and a ground line VSS. With the CMOS inverter 4B the output voltage of transistors TP and TN1 is inverted. The reference voltage is supplied by the reference voltage source 4A to the gate of transistor TN2. In general, the input voltage area of CMOS inverter 4B is very small, but its amplification factor is large. Consequently, it is needed to conform the input voltage of CMOS inverter 4B with the output voltage of memory cell 2. The input level of the first level shift amplifier is arranged based on the reference voltage. Thereby, the reference voltage source 4A to supply the reference voltage with the transistor TN2 is needed.
For another example, the level shift amplifier as shown in T.OOTANI, et aI., IEEE Journal of SOLID-STATE CIRCUITS, Vol. 25 No. 5 October 1990, pp. 1082-1092 (hereinafter called "the second level shift amplifier") comprises, as shown FIG. 2, a current mirror type sense amplifier 5, a Self-Aligned-Threshold-CMOS-Inverter 6, and p type field effect transistors TP11-TP13.
The current mirror type sense amplifier 5 comprises p type field effect transistors TP51 and TP52, and n type field effect transistors TN51-TN55, and reads the cell output voltage. A Self-Aligned-Threshold-CMOS-Inverter 6 comprises p type field effect transistors TP61 and TP62, and n type field effect transistors TN61-TN65, and amplifies the voltage detected by the sense amplifier 5.
At that point, the current mirror type sense amplifier of the second level shift amplifier has also a level shift function. A transistor TP13 is connected between the power voltage line VCC and the output of sense amplifier 5, and the output voltage of transistors TP52 and TN52 is adapted to the input voltage of Self-Aligned-Threshold-CMOS-Inverter 6.